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Home > chinese-english > "memory controller" in English

English translation for "memory controller"

存储控制器
存储器控制部
记忆控制器


Related Translations:
controller data:  控制器数据
credit controllers:  信贷控制人员
controller cache:  缓冲存储器控制器
controller cabinet:  控制柜
programming controller:  程序控制器
analyzer controller:  分析调节器分析控制器
sampling controller:  采样控制器抽样控制器取样控制器
braking controller:  制动控制器
monitor controller:  监督程序控制器监控程序控制器监控仪
application controller:  应用控制器
Example Sentences:
1.Gmch graphics memory controller hub
图形和内存控制中心
2.Gmch graphics memory controller hub
图形和内存控制中心
3.Crossbar - based memory controller
交叉内存控制器
4.I guess the most notable thing is putting the memory controller on the cpu chip , which has already been done by the alpha people , and has already been shown to have upsides and downsides
我想最值得注意的就是将存储器控制器放到cpu芯片上,这一点开发alpha的人员已经使用了,而且已经表现出有利也有弊。
5.It is designed for embedded applications with the following features : separate instruction and data caches ( harvard architecture ) , 5 - stage pipeline , hardware multiplier and divider , interrupt controller , 16 - bit i / o port and a flexible memory controller . new modules can easily be added using the on - chip amba ahb / apb buses . it has flexible peripheral interfaces , so can be used as an independent processor in the board - level application or as a core in the asic design
它遵照ieee - 1745 ( sparcv8 )的结构,针对嵌入式应用具有以下特点:采用分离的指令和数据cache (哈佛结构) ,五级流水,硬件乘法器和除法器,中断控制器, 16位的i / o端口和灵活的内存控制器,具有较强的异常处理功能,新模块可以轻松的通过片上的ambaahb / apb总线添加。
6.Memory controller design and ip interconnection are the common issues in system - on - a - chip ( soc ) design . having analyzed the established ip interconnection strategy and sgram characteristics , the author put forward the multi - agent momery interface interconnection strategy , defmed the interface protocol and implemented the momery interface design using finite state machines
存储器控制电路的设计和ip互连是soc设计中常遇到的问题。在分析了已有的ip互连机制和sgram特性后,本文给出多客户存储器接口的互连策略、定义了接口通信协议并且用状态机实现了该接口电路的设计。
7.Based on s698 technology , obt - devsys - s698 is one of the serial s698 - mil application development systems including 32 - bit embedded processor with 32 64 - bit fpu 160mhz processing speed sram memory controller flash memory controller uart ps 2 led interrupter controller , etc . the bus interfaces is composed of i2c spi magnetic card interface and ic card interface . obt - devsys - s698 carries on the advantages of s698 serial module such as compact structure and reasonable composition
Obt - devsys - s698是s698系列嵌入式处理器开发板中的一员,其上包括:具有32 64 - bit浮点运算单元的32 - bit嵌入式处理器,主频160mhz , sram存储器, flash存储器具有三路uart接口,一路ps 2接口, led发光二极管控制电路,中断操作按钮其外扩总线包括i2c总线接口spi总线接口磁卡接口智能卡接口等。
Similar Words:
"memory control and logging" English translation, "memory control logic" English translation, "memory control table" English translation, "memory control unit (mcu)" English translation, "memory control unit special register" English translation, "memory controller (memc)" English translation, "memory copy" English translation, "memory core" English translation, "memory core system" English translation, "memory core test" English translation